In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed. The High-Speed USB 2.0 Transceiver, which can be used with hosts, devices, or OTG function controllers, is implemented by the USB2.0 IP. The USB2.0 PHY IP specification, which supports Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates, comes after UTMI+level 3. High-speed data transport @ 480Mbps can be achieved by combining several mixed-signal circuits. The USB2.0 PHY IP also supports the enhanced USB Battery Charging standards, designed for use in consumer electronics and mobile devices.Numerous factories and nodes, including "TSMC 28HPC+, TSMC 40LP, TSMC 40LL, UMC 28HPC, UMC 40LP, UMC 55SP, UMC 55EF, SMIC 14SF+, SMIC 40LL, SMIC 55LL," implement the USB 2.0 PHY IP standard. Performance and data throughput were unaffected by the tiny chip size and low power consumption of the USB2.0 PHY IP transceiver. The USB2.0 PHY IP offers a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit in order to completely enable host and device functionality.
Deliverables
GDSII Physical Layout Representation with Layer Mapping Details
Representation of Placement and Routing Topology in .LEF
Repository of Timing and Power Models in Liberty Format
Functional Simulation Model in Verilog Language
SDF Timing Specifications Integrated into Circuit Connectivity Data
Guidelines for Successful Layout Construction and Adherence
Verification Reports Confirming Layout Schematic and Rule Conformance
