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IP Cores


T2M MIPI MIPI D-PHY Rx IP in 28HPC+

MIPI D-PHY Rx IP in 28HPC+

Description and Features

The MIPI D-PHY Analog RX IP Core complies exactly with version 1.2 of the D-PHY specification. The Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2) protocols are supported. One clock lane and four data lanes make up this RX PHY.

The D-PHY comprises of a digital back end to control the I/O operations and an analogue front end to produce and receive electrical level signals. Automatically calibrated internal termination resistor.

 

Features
  • Compliant to MIPI Alliance Standard for

  • D-PHY specification Version 1.2

  • Supports standard PPI interface compliant to MIPI Specification

  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s

  • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s

  • Supports ultra-low power mode, high speed mode and escape mode

  • Supports one clock lane and up to four data lanes

  • Data lanes support transfer of data in high speed mode

  • Supports error detection mechanism for sequence errors and contentions

  • Supports contention detection

  • Configurable skew option for each Clock and Data lanes

  • Testability for TX, RX and PLL

  • Silicon Proven in TSMC 28HPC+

Deliverables

  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behaviour model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports