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T2M › Verification IPs › 50G Base-KR/KR2 Ethernet VIP

50G Base-KR/KR2 Ethernet VIP

Description and Features

The 50GBase-KR/KR2 Ethernet Verification IP validates the MAC-to-PHY layer interfaces of designs using a 50G Base-KR/KR2 Ethernet interface in accordance with IEEE 802.3ba requirements. It can operate in environments that use SystemVerilog, Vera, SystemC, E, and Verilog HDL. Experts in Ethernet who have created Ethernet solutions for businesses like Intel, Cortina-Systems, Emulex, and Cisco have produced 50GBase-KR/KR2 verification IP. We are aware of the steps involved in verifying an Ethernet product. SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E, and non-standard verification environments all natively support the 50GBase-KR/KR2 Verification IP. The optional Smart Visual Protocol Debugger (Smart ViPDebug), a GUI-based debugger to expedite debugging, is included with 50GBase-KR/KR2 Verification IP.

50G-Base-KR-KR2-Ethernet-VIP-silicon-proven-ip-supplier-in-china

 

Features
  • Supports 50GBase-KR/KR2 interfaces as per the specifications defined in IEEE 802.3ba
  • Supports scrambler
  • Supports FEC
  • Supports backplane auto-negotation
  • Supports CDR for serial protocols
  • Supports MDIO slave and master model as per Clause 22 and Clause 45
  • Supports Glitch insertion and detection
  • Supports Pause frame generation and detection.
  • Supports all types of 50GBase-KR/KR2 TX and RX errors insertion/detection. • Oversize, undersize, inrange, out of range Packet size errors • Missing SPD/EPD/SFD framing errors • SFD on wrong lane • CRC Error • Lane skew insertion • Invalid /D/ and /K/ character injection • Variable preamble and IPG insertion • Invalid block code insertion • Sync bit corruption • FEC error injection • Scrambler error injection
  • Comes with 50GBase-KR/KR2 Tx BFM, 50GBase- KR/KR2 Rx BFM, and 50GBase-KR/KR2 PCS Monitor
  • Monitor supports detection of all protocol violations.
  • Built in coverage analysis.
  • Callbacks in master and slave for various events
  • Status counters for various events in bus

Deliverables

  • Complete regression suite containing all the testcases.
  • Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
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