Ethernet 40G PCS IP

Description

Ethernet 40G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 40G PCS IP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

Features

• Supports IEEE Standard 802.3.2018 Clause 82
• Supports 100GBASE-R
• Supports 64b/66b encoding and decoding for transmit and receive path
• Supports data scrambling on the transmit path and descrambling on the receive path
• Supports Lane Distribution across 20 Lanes for 40Gpbs
• Supports Block synchronization
• Supports Alignment Marker insertion and removal
• Support PCS Lane Deskew and Lane Re-ordering
• Supports BIP-8 insertion on transmit path and checking on receive path per lane
• Supports Bit Error Rate monitoring
• Supports receiver Link fault status detection
• Supports Loopback functionality
• Supports for IEEE 802.3az Energy Efficient Ethernet.
• Supports Configurable Management Interface (MDIO - Clause 45 / SOC Bus)
• Supports RS FEC as per clause 91 of IEEE Standard 802.3.2018
• Optional support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
• Programmable PRABS32 and PRABS9 test pattern generators and error checker
• Configurable Serdes interface
• Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

• A dedicated license tailored for businesses operating from a solitary location, providing exclusive access privileges.

• A versatile licensing solution designed for enterprises with a presence across multiple sites, facilitating widespread deployment.

• Permits the incorporation of the IP Core into a singular FPGA bitstream and ASIC, enabling precise implementation.

• Offers unrestricted utilization of the IP Core across numerous FPGA bitstreams and ASIC designs, fostering limitless innovation and adaptability.

Deliverables

• Executing Verilog RTL design implementation

• Verification scripts encompassing Linting, CDC analysis, and Synthesis, with waivers seamlessly integrated

• Elaborate reports providing detailed insights into Linting, CDC analysis, and Synthesis methodologies

• Employing IP-XACT RDL to generate an address map effectively

• Combining firmware code and Linux drivers into a unified package

• Comprehensive technical documentation covering all aspects thoroughly

• Verilog Test Environment featuring intuitively integrated test cases