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T2M MIPI MIPI DSI2 Tx v1.1 Controller IP

MIPI DSI2 Tx v1.1 Controller IP

Description and Features

MIPI is the Mobile Industry Processor Interface that provides specification for software and hardware interfaces in mobile terminals and thereby encouraging the adoption of these standards throughout the industry chain for achieving interoperability has come up with many specifications like CSI, DSI, DPHY, CPHY, MPHY, SoundWire, UniPro and more. The MIPI Display Serial Interface (DSI) is an interface between a display or any other data interface, and a host processor baseband application engine. This interface is defined by the MIPI Alliance, which lays down a series of modules required in a MIPI compliant product. MIPI DSI Receiver is leveraged by mobile and high–speed serial applications as a controller for receiving video, command or user data, transmitted via MIPI DSI Transmitter over MIPI lines. It is sent to the next, higher level for subsequent processing. The MIPI DSI Receiver, along with MIPI DSI Transmitter and MIPI DPHY, provides a complete solution for MIPI DSI communication.


  • Compliant with MIPI DSI-2 Standard v0.8.x, MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
  • Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios
  • Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
  • Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration
  • Forward and reverse communication
  • Configurable virtual channel up to 4
  • Function in continuous and non-continuous clock modes
  • Support for command and video mode
  • Support for burst and non-burst modes
  • Support for pulse and event modes
  • Color modes: 16, 18, 24 and 36 bpp
  • Support for display stream compression (dsc)


  • Configurable RTL Code
  • HDL-based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers, and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design guide
  • Verification guide
  • Synthesis guide
  • Highly modular and configurable design
  • Layered architecture
  • Active low async reset
  • Clearly de-marked clock domains
  • Extensive clock gating support
  • Wearables
  • Consumer
  • Automotive