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Semiconductor IP Cores

T2M › USB › USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 40LL

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 40LL

Description

The combined PHY complies with the PIPE, Serial ATA, PCIe, USB, USB 3.0, USB 2.0, and PCIe Peripheral Component Interconnect Express interface protocols (USB High-speed and Full speed). Supporting additional internal power gating, reference clock control, and PLL control allows for reduced power use. The PHY is also particularly advantageous for a range of situations under varied considerations of power consumption because of the adaptability of the previously described low power mode option.

 

Features
  • Compatible with PCIe/USB3/SATA base Specification
  • Fully compatible with PIPE3.1 interface specification
  • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
  • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • Support 20-bit parallel interface when encode/decode bypassed
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm
  • Support programmable transmit amplitude and De-emphasis
  • Support TX detect RX function in PCIe and USB3.0 Mode
  • Support Beacon signal generation and detection in PCIe Mode
  • Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
  • Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode
  • Support L1 sub-state power management
  • Support RX low latency mode in SATA operation mode
  • Support Loopback BERT and Multiple Pattern BIST Mode
  • HPC Plus 0.9V/1.8V 1P8M
  • ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA
  • Silicon Proven in SMIC 40LL

Deliverables

  • Physical Layout Representation with Layer Assignment in GDSII

  • Representation of Placement and Routing Topology in

  • .LEF Repository of Timing and Power Models in Liberty Format

  • Functional Simulation Model in Verilog Syntax

  • SDF Timing Specifications Embedded within Circuit Netlist

  • Guidelines for Successful Layout Execution and Compliance

  • Verification Reports Confirming Layout Schematic and Rule Conformance

Application

  • PC
  • Television
  • Data Storage
  • Multimedia Devices
  • Recorders
  • Mobile Devices
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