Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M › Verification IPs › 800G Ethernet VIP

800G Ethernet VIP

Description and Features

The 800GBase-KR16 Ethernet Verification IP validates designs using an 800G Base-KR16 Ethernet interface's MAC-to-PHY layer interface in accordance with IEEE 802.3bs requirements. It can operate in environments that use SystemVerilog, Vera, SystemC, E, and Verilog HDL. Experts in Ethernet who have created Ethernet solutions for businesses like Intel, Cortina-Systems, Emulex, and Cisco are behind the development of the 800GBase-KR16 verification IP. We are aware of the steps involved in verifying an Ethernet product. An optional Smart Visual Protocol Debugger, a GUI-based debugger that speeds up debugging and is natively supported with SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E, and non-standard verification environments, is included with the 800G Ethernet Verification IP.

800G-Ethernet-VIP-silicon-proven-ip-supplier-in-taiwan

 

Features
  • Supports 800GBase-KR16 interface as per the specification defined in IEEE 802.3bs
  • Supports 800GMII
  • Supports scrambler
  • Supports FEC
  • Supports backplane auto-negotation
  • Supports Upper layer protocols.
  • Supports IP in IP
  • Supports Q in Q
  • Supports CDR for serial protocols
  • Supports MDIO slave and master model as per Clause 22 and Clause 45
  • Supports Pause frame generation and detection.
  • Supports Glitch insertion and detection
  • Supports all types of 800GBase-KR16 TX and RX errors insertion/detection. • Oversize, undersize, inrange, out of range Packet size errors • Missing SPD/EPD/SFD framing errors • SFD on wrong lane • CRC Error • Lane skew insertion • Invalid /D/ and /K/ character injection • Variable preamble and IPG insertion • Invalid block code insertion • Sync bit corruption • FEC error injection • Scrambler error injection
  • Comes with 800GBase-KR16 Tx BFM, 800GBase- KR16 Rx BFM and 800GBase-KR16 PCS Monitor
  • Monitor supports detection of all protocol violations.
  • Built in coverage analysis.
  • Callbacks in master and slave for various events
  • Status counters for various events in bus

Deliverables

  • Complete regression suite containing all the testcases.
  • Examples showing how to connect various components and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
Request Datasheet