Description and Features
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps. It conforms with the standards of UTMI+ and PIPE4.0. The USB 3.2 Gen2X1 IP features high-speed mixed signal circuits to support Gen2 and Gen1 traffic and is backward compatible with high-speed data rates of 480Mbps, full-speed data rates of 12Mbps, and low-speed data rates of 1.5Mbps. The USB 3.2 Gen2X1 IP provides an active switch to enable bi-directional plug-in and particular functionality (such VBUS setup and USB attachment cable orientation detection) through the CC1/CC2 pins specified in the Type-C connection in order to support the USB Type-C connector.

Features
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Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
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Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
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Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
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Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
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Integrates an active switch to support the orientation-less connection with USB Type-C connector
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Provides an auxiliary CC module IP to support USB Type-C related functions
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Supports both wire-bond and flip-chip package type
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Silicon Proven in TSMC 16FFC
Deliverables
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GDSII & layer map
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Place-Route views (.LEF)
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Liberty library (.lib)
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Verilog behaviour model
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Netlist & SDF timing
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Layout guidelines, application notes
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LVS/DRC verification reports