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T2M USB USB 3.1 Type-C PHY IP in 55LL

USB 3.1 Type-C PHY IP in 55LL

Description and Features

The USB3.1Type-C PHY is a high-speed, SERDES IP with high performance that was created for semiconductors that allow high-bandwidth, low-power data transfers. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A separate PCS can be provided in addition to the USB 3.1 Type C PHY IP to fulfil the functions of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing. Depending on the needs of the customer, PCS is offered as a hard macro or a soft macro. The PCS standard will also be made available on its own. PHY functionality is verified by the NC-Verilog simulation tool using a test bench created in Verilog HDL..


  • Support half rate mode (5Gbps) and full rate mode (10Gbps)

  • Tolerate max +/-7000ppm input frequency offset

  • 32bit/40bit selectable parallel data bus

  • Programmable transmit amplitude

  • 3 taps/2 taps selectable FFE

  • Receiver CTLE and One-tap perspective DFE

  • Build in self-test with PRBS7/31 pattern generation and checker for production test

  • Integrated on-die termination resistors

  • Support receiver detection

  • Support LFPS signal generation and detection

  • Support Spread Spectrum clock generation and receiving

  • Flexible reference clock frequency

  • Do not need any external component

  • ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA

  • Metal Layer:M1~M7+RDL

  • Core Voltage: 1.1V

  • IO Voltage: 3.3V

  • Silicon Proven in SMIC 55LL


  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behavior model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports