Description
The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ process technology, complies with the most recent JEDEC requirements, is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.
Features
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Supported DRAM type: DDR3L/DDR4/LPDDR4
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Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
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Interface: SSTL135/POD12/LVSTL
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Data path width scales in 32-bit increment
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Four modules for flexible configuration:CA/DQ_X16/DQ_X8/ZQ
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Programmable output impedance (DS)
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Programmable on-die termination (ODT)
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Core power:0.9V, I/O power (VDDQ):1.5V/1.35V/1.2V, RX power:1.8V
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ESD: 2KV/HBM, 200V/MM, 500V/CDM
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Support ZQ calibration
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Support 8 ranks
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Support write-leveling, CBT
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Support PHY internal VREFDQ auto decision
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Per-bit deskew in read and write datapath
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Silicon Proven in UMC 28HPC+ process technology
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Supported metal scheme: 1P7M_1C
Deliverables
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Application Note / User Manual
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Behavior model, and protected RTL codes
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Protected Post layout netlist and Standard Delay Format (SDF)
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Frame view (LEF)
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Metal GDS (GDSII)
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Test patterns and Test Documentation
