Description and Features
I2S Verification IP provides an smart way to verify the I2S bi-directional two-wire bus. The I2S Verification IP is fully compliant with version Philip's I2S-Bus Specification June 5, 1996 and provides the following features. I2S Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env I2S Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.
Features
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Complies with Philips I2S Specification June 5, 1996
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Full I2S Transmitter, Receiver and Controller functionality
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Supports up to 32 channels in transmit path
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Supports up to 32 channels in receive path
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Supports programmable word length 8, 12, 16, 20, 24, 32
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Supports programmable padding
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Supports programmable bit reversal
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Supports left and right justified
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Both transmitter and receiver can either work with SCK as input or can drive SCK
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Supports programmable data rate on transmit path • Can operate as master or slave in several configurations • Master or slave mode as transmitter • Master or slave mode as receiver • Master mode as controller (does not transmit or receive data) • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
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Status counters for various events on bus.
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Callbacks in transmitter, receiver and monitor for various events.
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Supports constraints Randomization.
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Built in functional coverage analysis.
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I2S Verification IP comes with complete test suite to test every feature of I2S specification.
Deliverables
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Complete regression suite containing all the I2S testcases.
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Examples showing how to connect various components, and usage of Master, Slave and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes
