Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores


T2M USB USB 2.0 PHY IP in 40LL

USB 2.0 PHY IP in 40LL

Description and Features

The USB 2.0 PHY IP Core is a complete solution for the physical layer (PHY) that prioritizes both high performance and low power consumption. This versatile IP core offers a High-Speed USB 2.0 transceiver compatible with host, device, and On-The-Go (OTG) function controllers. Compliant with the UTMI+ level 3 specification, the USB2.0 PHY IP also supports legacy data rates of Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps). A combination of advanced mixed-signal circuits enables high-speed data transmission at 480 Mbps. Additionally, the USB2.0 PHY IP supports the latest USB Battery Charging specifications, making it ideal for mobile and consumer electronics. Despite its small size and low power consumption, the USB2.0 PHY transceiver maintains excellent performance and data throughput. For comprehensive functionality as both a host and device, the USB2.0 PHY IP provides a complete on-chip physical transceiver solution with features like Electrostatic Discharge (ESD) protection, an internal PLL for clock generation, and a resistor termination calibration circuit.

 
 
 

Features
  • Compliant with USB2.0 and USB1.1 specification
  • Compliant with UTMI Specification Version level 3.
  • Supports HS (480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
  • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
  • 16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS
  • Serializing for transmitting data stream and Deserializing for receiving data stream
  • USB Data Recovery and Clock Recovery on receiving
  • Integrated Bit Stuffing and NRZI encoding for Transmit
  • Integrated Bit Un-Stuffing and NRZI decoding for Receive
  • SYNC and EOP generation on transmit packets and detection on receive packets
  • Internal reference resistor that replaces the external reference resistor
  • Built in self test for production testing
  • Supports USB suspend state and remote wakeup
  • Supports detection of USB reset, suspend and resume signaling
  • Supports high speed identification and detection as defined by USB 2.0 Specification
  • Support high speed host disconnection detection
  • Silicon Proven in SMIC 40LL

Deliverables

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation