For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered. The PHY complies with the UTMI, USB 2.0 PIPE, and USB 3.0 (USB SuperSpeed) requirements. The USB3.0 PHY IP transceiver is designed to consume little power and take up little space on the chip without compromising speed or data throughput. The USB3.0 PHY IP includes a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalization circuit to ensure full support for high-performance designs. Multiple IP sources are supported by the USB3 MAC layer over the shared PHY interface (PIPE). Internal test monitoring and permitted modification of analogue circuit parameters Using consistent power, built-in Self-Test, integrated Jitter Injection Output and jitter is minimised.