Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores


USB 3.0 PHY IP in 22ULP

Description and Features

The USB 3.0 PHY IP Core is a transceiver provided for supplementary devices, compliant with UTMI (USB SuperSpeed), USB 3.0, and USB 2.0 PIPE requirements. With minimal power consumption and chip area requirements, the USB3.0 PHY IP transceiver doesn't sacrifice speed or data throughput. The USB3.0 PHY IP offers complete support for high-performance designs by offering an integrated self-test module with integrated jitter injection, a dynamic equalization circuit, and a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection. Multiple IP sources can use the same PHY interface (PIPE) thanks to the USB3 MAC layer. Constant power, integrated Jitter Injection Output, integrated Self-Test, and approved customization of analog circuit characteristics remove internal test monitoring and jitter.


  • Compliant with Universal Serial Bus 3.0 Specification
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Compliant with PIPE 3.0
  • Compliant with Universal Serial Bus 2.0 Specification
  • High-speed data transfer rate: 480 Mbps
  • Compliant with legacy USB 1.1
  • Full-speed data transfer rate: 12 Mbps
  • Compliant with UTMI 1.05 Specification
  • Operating Voltage: 1.1V and 3.3V
  • Support low jitter automatically calibrated oscillator for crystal-less mode
  • Support 125/250 MHz with 32/16-bit mode for USB 3.0
  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing
  • Silicon Proven in TSMC 22ULP


  • Graphic Data System II File with Layer Configuration

  • Layout Exchange Format for Placement and Routing Visualizations

  • Standard Cell Library in Liberty Format

  • Functional Model in Verilog HDL

  • Circuit Description with SDF Timing Annotations

  • Guidelines and Recommendations for Layout Design

  • Reports on Layout Verification for Schematic and Design Rule Compliance