The USB 3.0 PHY IP Core is a transceiver provided for supplementary devices, compliant with UTMI (USB SuperSpeed), USB 3.0, and USB 2.0 PIPE requirements. With minimal power consumption and chip area requirements, the USB3.0 PHY IP transceiver doesn't sacrifice speed or data throughput. The USB3.0 PHY IP offers complete support for high-performance designs by offering an integrated self-test module with integrated jitter injection, a dynamic equalization circuit, and a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection. Multiple IP sources can use the same PHY interface (PIPE) thanks to the USB3 MAC layer. Constant power, integrated Jitter Injection Output, integrated Self-Test, and approved customization of analog circuit characteristics remove internal test monitoring and jitter.
Deliverables
Graphic Data System II File with Layer Configuration
Layout Exchange Format for Placement and Routing Visualizations
Standard Cell Library in Liberty Format
Functional Model in Verilog HDL
Circuit Description with SDF Timing Annotations
Guidelines and Recommendations for Layout Design
Reports on Layout Verification for Schematic and Design Rule Compliance
