Ethernet 25G TSN MAC IP

Description and Features

Ethernet 25G TSN MAC core is a full-featured, easyto- use, synthesizable design that supports various Ethernet TSN IEEE standards. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 25G TSN MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

Features

• Compliant with IEEE Standard 802.3-2018 Specification - Clause 106
• Supports Pre-emption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
• Supports timing synchronization as per IEEE Standard 1588-2008(PTP) and IEEE Standard 802.1AS(GPTP)
• Supports Traffic Scheduling - IEEE Standard 802.1Qbv (Enhancement for Scheduled Traffic) and IEEE Standard 802.1Qav (Credit Based Shaping)
• Supports class-based flow control and class-based FIFO to store each class, total 8 class - IEEE Standard 802.1Q
• Supports Full duplex mode of operation
• Ultra-low latency and compact implementation
• Supports MDIO (Clause 22 and Clause 45) Interface
• Supports Programmable Inter Packed Gap (IPG) and Preamble length
• Supports XGMII (32 bit) interface
• FCS generation supported
• Supports VLAN and jumbo frames as an option
• Independent TX and RX Maximum Transmission Unit (MTU)
• TSN features can be enabled/disabled independently
• Cut-through support
• Configurable Transmit and Receive FIFOs
• Comprehensive statistics gathering
• Supports 32bit AXI4 Stream for Packet data
• In house UNH compliance tested
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

• Tailored licensing solution for enterprises operating from a single location, providing focused access.

• Versatile licensing option for organizations with operations across multiple sites, ensuring comprehensive coverage.

• Enables integration of the IP Core into a solitary FPGA bitstream and ASIC, facilitating specific implementation.

• Unrestricted usage of the IP Core across an extensive range of FPGA bitstreams and ASIC designs, fostering expansive flexibility and innovation.

Deliverables

• Executing Verilog RTL implementation

• Validation scripts encompassing Linting, CDC analysis, and Synthesis, incorporating waivers

• Elaborate reports offering insights into Linting, CDC analysis, and Synthesis procedures

• Generating an address map utilizing IP-XACT RDL

• Bundling firmware code and Linux drivers into a unified package

• Thorough technical documentation covering all facets comprehensively

• Verilog Test Environment featuring seamlessly integrated intuitive test cases