Description and Features
The MIPI DPHY Verification IP validates DPHY devices and is MIPI DPHY standard compliant. Experts that have previously worked on difficult protocols have created DPHY Verification IP. Verilog, SystemC, VERA, Specman E, VMM, RVM, AVM, OVM, UVM, and non-standard verification environments all natively support the MIPI DPHY Verification IP. The Smart Visual Protocol Debugger, a GUI-based debugger to expedite debugging, is an optional component of the MIPI DPHY Verification IP.
Features
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Full MIPI DPHY Transmitter and Receiver functionality.
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Supports 3.0 MIPI DPHY Specifications.
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Supports both serial and PPI functionality testing.
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Supports short and long packets
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Supports BTA operations.
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Supports all lane configuration
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Supports multiple packets per transmission
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Supports Skew Calibration.
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Supports Alternate Calibration Sequence.
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Supports Preamble Sequence.
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Supports HS-Idle state in serial and PPI mode.
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Supports differential and single ended mode of operation
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Various kind of Transmitter and Receiver errors generation and detection • SoT Error • SoT Sync Error • EoT Sync Error
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Escape Entry Command Error
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LP Transmission Sync Error
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False Control Error
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Status counters for various events in bus.
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Operates as a Transmitter, Receiver
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Monitor, Detects and notifies the test bench of all protocol and timing errors.
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Callbacks in node transmitter, receiver and monitor for user processing of data.
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MIPI DPHY Verification IP comes with complete test suite to test every feature of MIPI DPHY specification.
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Functional coverage for complete MIPI DPHY features
Deliverables
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Complete regression suite containing all the MIPI DPHY testcases.
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Examples showing how to connect various components, and usage of Tx, Rx and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes
