MIPI DPHY Verification IP is compliant with MIPI DPHY specification and verifies DPHY devices. DPHY Verification IP is developed by experts who have worked on complex protocols before. MIPI DPHY Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env. MIPI DPHY Verification IP comes with optional Smart Visual Protocol Debugger, which is GUI based debugger to speed up debugging.
Full MIPI DPHY Transmitter and Receiver functionality.
Supports 3.0 MIPI DPHY Specifications.
Supports both serial and PPI functionality testing.
Supports short and long packets
Supports BTA operations.
Supports all lane configuration
Supports multiple packets per transmission
Supports Skew Calibration.
Supports Alternate Calibration Sequence.
Supports Preamble Sequence.
Supports HS-Idle state in serial and PPI mode.
Supports differential and single ended mode of operation
Various kind of Transmitter and Receiver errors generation and detection • SoT Error • SoT Sync Error • EoT Sync Error
Escape Entry Command Error
LP Transmission Sync Error
False Control Error
Status counters for various events in bus.
Operates as a Transmitter, Receiver
Monitor, Detects and notifies the test bench of all protocol and timing errors.
Callbacks in node transmitter, receiver and monitor for user processing of data.
MIPI DPHY Verification IP comes with complete test suite to test every feature of MIPI DPHY specification.
Functional coverage for complete MIPI DPHY features
Complete regression suite containing all the MIPI DPHY testcases.
Examples showing how to connect various components, and usage of Tx, Rx and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes