The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwidth data transfers. The USB 3.1Type-C PHY IP is a particular design for USB 3.1 type-C applications. To fulfil the functionality of various applications, such as elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing, a separate PCS can be offered in addition to the USB 3.1 Type C PHY IP. PCS is available as a hard macro or a soft macro, depending on the customer's need. Additionally, the PCS standard will be made independently accessible. The NC-Verilog simulation program validates PHY functionality using a test bench developed in Verilog HDL.
Deliverables
Layer Mapping Information in GDSII Format
Visual Representation of Placement and Routing in LEF Format .
lib File Containing Timing, Power, and Noise Information
Functional Model Expressed in Verilog Syntax
Standard Delay Format Timing Information Applied to Circuit Netlist
Design Guidelines for Layout Implementation and Optimization
Validation Reports Ensuring Layout Consistency and Rule Conformance
