Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M USB USB 3.1 Type-C PHY IP in 14SF+

USB 3.1 Type-C PHY IP in 14SF+

Description and Features

The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwidth data transfers. The USB 3.1Type-C PHY IP is a particular design for USB 3.1 type-C applications. To fulfil the functionality of various applications, such as elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing, a separate PCS can be offered in addition to the USB 3.1 Type C PHY IP. PCS is available as a hard macro or a soft macro, depending on the customer's need. Additionally, the PCS standard will be made independently accessible. The NC-Verilog simulation program validates PHY functionality using a test bench developed in Verilog HDL.


  • Support half rate mode (5Gbps) and full rate mode (10Gbps)

  • Tolerate max +/-7000ppm input frequency offset

  • 32bit/40bit selectable parallel data bus

  • Programmable transmit amplitude

  • 3 taps/2 taps selectable FFE

  • Receiver CTLE and One-tap perspective DFE

  • Build in self-test with PRBS7/31 pattern generation and checker for production test

  • Integrated on-die termination resistors

  • Support receiver detection

  • Support LFPS signal generation and detection

  • Support Spread Spectrum clock generation and receiving

  • Flexible reference clock frequency

  • Do not need any external component

  • ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA

  • Metal Layer:M1~M7+RDL

  • Core Voltage: 1.1V

  • IO Voltage: 3.3V

  • Silicon Proven in SMIC 14SF+


  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behavior model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports