12-bit successive approximation Analog-to-Digital Converter (ADC) is designed for high-performance applications. Utilizing 28FDSOI technology with process options including 6 Metal (5+1), 8 Metal (6+2), and 10 Metal (6+2+2), this ADC achieves exceptional performance while maintaining a compact silicon footprint. With a parallel 12-bit output, this ADC offers a conversion time of 1 µs and a sampling frequency of 1 Msps, making it suitable for applications requiring fast and accurate analog-to-digital conversion. In terms of performance, the ADC delivers exceptional accuracy with Integral Non-Linearity (INL) of less than ±2 LSB and Differential NonLinearity (DNL) of less than ±1 LSB, ensuring precise conversion of analog signals into digital data. Overall, this ADC offers high-performance analogto-digital conversion in a compact and efficient package, making it ideal for a wide range of applications including industrial automation, medical imaging, and telecommunications.
1. 12-bit Parallel Output.
2. Conversion time/Sampling frequency = 1 us/ 1Msps
3. CLOCK REQUIREMENT: 2 MHz- 20 MHz
4. SUPPLY REQUIREMENT: 1.8 V Analog/1.0 V Digital
5. PERFORMANCE PARAMETERS:
-INL
a. Typ= +/- 2 LSB
b. Max= +/- 4 LSB
-DNL
c. Typ= +/- 1 LSB
d. Max= +/- 2 LSB
-EOB
e. Typ= +/- 10 LSB
f. Max= +/- 20 LSB
-EOT
g. Typ= +/- 10 LSB
h. Max= +/- 20 LSB
-ANALOG INPUT FREQUENCY
i. Typ= 100 KHz
-SNDR (Fin=100Khz,Fs=1MHz)
j. Min= 54 dB
k. Typ= 60 dB
6. Process option: 6 Metal (5+1),8 metal (6+2) and 10 Metal (6+2+2)
7. TEMPERATURE RANGE: Min= -40, Typ= 25, Max= 125
8. Silicon Proven in 28FDSOI
9. Production Proven
Deliverables
Detailed Datasheet
Verilog behavior model (A) for simulation
Liberty (db./.lib) for synthesis, STA, and equivalence checking
CTL / CTLDB for DFT
SPF (Standard Test Interface Language (STIL Procedure File) for ATPG
LEF for APR
CDL for LVS connection
Benefits
Low area and low power
Excellent linearity
Compact area
Applications
Medical Application
Ethernet
Automotive
Communication system
Microcontrollers
Sensors
