Description
The DDR3 component of a SOC or ASIC may be intelligently verified with the help of DDR3 Monitor. The DDR3 Monitor offers the following characteristics and complies fully with the DDR3 Specification.DDR3 Monitor Verification IP is supported natively in System Verilog, VMM, RVM, AVM, OVM, UVM, Verilog, System C, VERA, Specman E and non-standard verification env DDR3 Monitor Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.
Features
-
Supports DDR3 memory devices from all leading vendors
-
Quickly validates the implementation of the DDR3 standard
-
Constantly monitors DDR3 behavior during simulation
-
Checks for following • Check-points include Initialization rules, • State based rules, Active Command rules, • Read/Write Command rules etc.
-
Support for full-timing as well as behavioral versions in one model
-
Support for all timing delay ranges in one model: min, typical and max
-
Built in coverage analysis
-
Supports Callbacks, so that user can access the data observed by monitor.
Deliverables
-
Complete regression suite containing all the DDR3 testcases.
-
Examples showing how to connect and usage of Monitor.
-
Detailed documentation of all class, task and function's used in verification env.
-
Documentation also contains User's Guide and Release notes
