The GPHY is a highly integrated IP Core for low- power Gigabit Ethernet applications. It is capable of operating at 10BASE-T, 100BASE-TX, and 1000BASE-T. The GMII (Giga Media Independent Interface) connects this GPHY to the Media Access Control Layer (MAC). This GPHY links to the Media Access Control Layer (MAC) through GMII or RGMII. It may handle Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet and 1000BASE-T Giga Ethernet, as well as UTP5/UTP3 cable for 10BASE-Te Ethernet. It covers the complete physical layer function of 100BASE-TX specified by IEEE802.3u and 1000BASET defined by IEEE802.3ab, including the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), and Twisted Pair Physical Medium Dependent Sub-layer (TP-PMD, 100BASE- TX only).
IEEE 802.3-2008, IEEE 802.3az fully standards compliant
IEEE 1588-2008 support
BroadR-Reach™ support
Dual port MAC interface:
GMII (10/100/1000BASE-T)
MII (10/100BASE-T).
Auto-negotiation support
Automatic detection and correction of pair swaps (Auto-MDIX), pair skew and pair polarity
6 different operating modes:
1000BASE-T Full Duplex and Half Duplex
100BASE-TX Full Duplex and Half Duplex
10BASE-T Full Duplex and Half Duplex
Management interface
Baseline wander compensation
On-chip transmit wave-shaping
On-chip hybrid circuit
10KB jumbo frames
Internal, external and remote loop back
Hardware configuration for default operation
Power down mode, interrupt support
IEEE 1500 support for SoC testing integration.
LED indication: link mode, status, speed, activity, and collision
Silicon Proven in TSMC 12nm FFC.
Deliverables
Comprehensive Data Sheet
Verilog Simulation Behavior Model (A)
Liberty Files (db/.lib) for Synthesis, Static Timing Analysis (STA), and Equivalence Checking
Design for Testability (DFT) with CTL/CTLDB
ATPG (Automatic Test Pattern Generation) using SPF (STIL Procedure File)
LEF Files for Automatic Place and Route (APR)
CDL for Layout Versus Schematic (LVS) Connection
