The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, devices, or OTG function controllers, the USB2.0 IP implements a High-Speed USB 2.0 transceiver. The USB2.0 PHY IP is compatible with Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates and complies with the UTMI+ level 3 specification. It integrates mixed-signal circuits to support High-Speed data rate at 480Mbps. The USB2.0 PHY IP also supports the additional USB Battery Charging requirements, which are aimed at mobile and consumer product applications. The USB2.0 PHY IP transceiver is designed to have a small chip size and low power consumption without compromising performance or data throughput. To enable complete support for host and device functionality, the USB2.0 PHY IP includes a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination
calibration circuit.
Compliant with USB2.0 and USB1.1 specification
Compliant with UTMI Specification Version level 3.
Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS
Serializing for transmitting data stream and Deserializing for receiving data stream
USB Data Recovery and Clock Recovery on receiving
Integrated Bit Stuffing and NRZI encoding for Transmit
Integrated Bit Un-Stuffing and NRZI decoding for Receive
SYNC and EOP generation on transmit packets and detection on receive packets
Internal reference resistor that replaces the external reference resistor
Built in self test for production testing
Supports USB suspend state and remote wakeup
Supports detection of USB reset, suspend and resume signaling
Supports high speed identification and detection as defined by USB 2.0 Specification
Support high speed host disconnection detection
Silicon Proven in TSMC 28HPC+
Deliverables
Application Note / User Manual
Behavior model, and protected RTL codes
Protected Post layout netlist and Standard
Delay Format (SDF)
Frame view (LEF)
Metal GDS (GDSII)
Test patterns and Test Documentation
