Description
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth, Equalizer Strength, Terminator Resistor, and BGR Voltage, up to 5.4 Gbps per channel (HBR2). It also includes testability options such as PLL alone test and analog signal monitor, ensuring comprehensive functionality for signal processing and testing in digital display systems.
Features
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DisplayPort version 1.4 compliant receiver
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PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate
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Integrated 100-ohm termination resistors with common-mode biasing
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Integrated equalizer with tunable strength
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eDP version 1.4a / DP version 1.3 compliant
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receiver Supports HDCP1.4 and HDCP2.2(Optional)
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Consists of configurable (4/2/1) link channels and one AUX channel
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Supports 1.62Gbps (RBR), 5.4Gbps (HBR2) and 8.1 Gbps (HBR3) bit rate
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Supports main link operation with 1 or 2 or 4 lanes
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Supports both Default and Enhanced Framing Mode Supports SST mode
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Supports video packet and audio packet
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Supports 18 / 24-bit RGB digital video output format Master I2C interface for DDC connection
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Interface to external HDCP key storage
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Configuration registers programmable via AMBA interface
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Configurable analog characteristics
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CDR bandwidth
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Equalizer strength
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Terminator resistance
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BGR voltage
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Regulator voltage
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Support PLL test and internal analog signal monitor
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1.8V/0.9V power supply
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Silicon Proven in TSMC 40nm LP.
Deliverables
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Verilog RTL or netlist source code of LINK controller.
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Abstracted timing models for synthesis and STA
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Timing constrains for synthesis and physical layout
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Behavioral Verilog Model, simulation test bench, run control scripts, and test stimuli
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Physical design database
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Integration guidelines
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Reference software sample code
