USB 3.2 Device Controller which essentially handles 2lanes each 10GBps. USB 3.2 Device controller is a highly configurable core and implements the USB 3.2 Device functionality that can be interfaced with third party USB 3.2 PHY’s. USB3.2 Device controller core is part of USB3.0 family of cores. The Device Controller core is architected with an high performance DMA engine based on USB3.2 specification. The Device Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.
This controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications. This Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc. 
Customizable Register Transfer Level (RTL) Implementation
Hardware Description Language (HDL) Test Environment with Behavioral Models
Test Suites and Scenarios
Protocol Verification Tools, Bus Monitors, and Performance Analyzers
Adaptable Synthesis Framework
Design Reference Handbook
Verification Instruction Guide
Synthesis Process Manual
FPGA Validation Platform for Pre-Tape-out Verification
Firmware Blueprint and Reference Implementation
