Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M Verification IPs 400G Base-KR4/KR8/KR16 Ethernet VIP

400G Base-KR4/KR8/KR16 Ethernet VIP

Description and Features

The 400GBase-KR4/KR8/KR16 Ethernet Verification IP is compliant with IEEE 802.3bs specifications and verifies MAC-to-PHY layer interfaces of designs with a 400GBase-KR4/KR8/KR16 Ethernet interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. 400GBase-KR4/KR8/KR16 verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product. 400GBase-KR4/KR8/KR16 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and nonstandard verification env . 400GBase-KR4/KR8/KR16 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging

400G-Base-KR4-KR8-KR16-Ethernet-VIP-silicon-proven-ip-supplier-in-china

 

Features
  • Supports scrambler
  • Supports FEC
  • Supports backplane auto-negotation
  • Supports CDR for serial protocols
  • Supports MDIO slave and master model as per Clause 22 and Clause 45
  • Supports Glitch insertion and detection
  • Supports Pause frame generation and detection.
  • Supports all types of 50GBase-KR/KR2 TX and RX errors insertion/detection. • Oversize, undersize, inrange, out of range Packet size errors • Missing SPD/EPD/SFD framing errors • SFD on wrong lane • CRC Error • Lane skew insertion • Invalid /D/ and /K/ character injection • Variable preamble and IPG insertion • Invalid block code insertion • Sync bit corruption • FEC error injection • Scrambler error injection
  • Comes with 50GBase-KR/KR2 Tx BFM, 50GBase- KR/KR2 Rx BFM, and 50GBase-KR/KR2 PCS Monitor
  • Monitor supports detection of all protocol violations.
  • Built in coverage analysis.
  • Callbacks in master and slave for various events
  • Status counters for various events in bus

Deliverables

  • Complete regression suite containing all the testcases.
  • Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.