Description and Features
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogue features, 100-ohm termination resistors, and common-mode biassing the CDR bandwidth, the regulator voltage, the BGR voltage, and the terminator resistance Support 1.8V/0.9V power supplies for internal analogue signal monitoring and PLL testing.

Features
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eDP version 1.4a / DP version 1.4 compliant transmitter
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Supports HDCP1.4 and HDCP2.2(Optional)
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Supports Forward Error Correction (Optional)
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Consists of configurable (4/2/1) link channels and one AUX channel
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Supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate (ie 2.16Gbps etc)
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Supports main link operation with 1 or 2 or 4 lanes
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Supports both Default and Enhanced Framing Mode
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Supports SST mode
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Supports video packet and audio packet (8ch max)
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Supports both Normal and Alternate Scrambler Seed Reset
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Supports E-EDID data reading via I2C-over-AUX transaction
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Supports Video test pattern generator (compliant with DP link CTS v1.2)
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Configuration registers programmable via AMBA interface
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Silicon Proven in TSMC 28HPC+
Deliverables
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Verilog RTL or netlist source code of LINK controller.
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Abstracted timing models for synthesis and STA
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Timing constrains for synthesis and physical layout
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Behavioural Verilog Model, simulation test bench, run control scripts, and test stimuli
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Physical design database
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Integration guidelines
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Reference software sample code