A Universal Serial Bus (USB) transceiver is available for auxiliary devices. The PHY complies with the UTMI, USB 3.0, and USB 2.0 PIPE requirements (USB SuperSpeed). Without sacrificing speed or data throughput, the USB3.0 PHY IP transceiver is made to use little power and occupy little space on the chip. The USB3.0 PHY IP offers complete support for high-performance designs by offering a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, an integrated self-test module with built-in jitter injection, and a dynamic equalization circuit. Numerous IP sources can use the same PHY interface thanks to the USB3 MAC layer (PIPE). Constant power, built-in Jitter Injection Output, built-in Self-Test, and allowed customization of analogue circuit properties remove internal test monitoring and jitter.
Deliverables
GDS2 File Containing Layer Information
Design Views for Placement and Routing Topology
Liberty Format Library for Timing and Power Models
Verilog Model for Functional Analysis
Circuit Connectivity with Timing Specifications in SDF
Layout Design Considerations and Application Guidance
Verification Reports for Layout Schematic and Design Rule Checks
