Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.0 PHY IP in 40LP

USB 3.0 PHY IP in 40LP

Description and Features

A Universal Serial Bus (USB) transceiver is available for auxiliary devices. The PHY complies with the UTMI, USB 3.0, and USB 2.0 PIPE requirements (USB SuperSpeed). Without sacrificing speed or data throughput, the USB3.0 PHY IP transceiver is made to use little power and occupy little space on the chip. The USB3.0 PHY IP offers complete support for high-performance designs by offering a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, an integrated self-test module with built-in jitter injection, and a dynamic equalization circuit. Numerous IP sources can use the same PHY interface thanks to the USB3 MAC layer (PIPE). Constant power, built-in Jitter Injection Output, built-in Self-Test, and allowed customization of analogue circuit properties remove internal test monitoring and jitter.


  • Compliant with Universal Serial Bus 3.0 Specification
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Compliant with PIPE 3.0
  • Compliant with Universal Serial Bus 2.0 Specification
  • High-speed data transfer rate: 480 Mbps
  • Compliant with legacy USB 1.1
  • Full-speed data transfer rate: 12 Mbps
  • Compliant with UTMI 1.05 Specification
  • Operating Voltage: 1.1V and 3.3V
  • Support low jitter automatically calibrated oscillator for crystal-less mode
  • Support 125/250 MHz with 32/16-bit mode for USB 3.0
  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing
  • Silicon Proven in TSMC 40LP.


  • GDS2 File Containing Layer Information

  • Design Views for Placement and Routing Topology

  • Liberty Format Library for Timing and Power Models

  • Verilog Model for Functional Analysis

  • Circuit Connectivity with Timing Specifications in SDF

  • Layout Design Considerations and Application Guidance

  • Verification Reports for Layout Schematic and Design Rule Checks