Smart card controller core is compliant to ISO 7816 3 specification. The core is a technology independent, fully synchronous design. The controller functions at 2 –66 Mhz. The design provides a simple, timing friendly front end interface which enables easy integration of the core to controllers and other application specific front end logic. The controller supports smart cards with internal clocks and internal resets. It has a well defined, easy to integrate processor interface. The design has hardware support for activation, deactivation and data transfer. It also supports hardware initiated smart card deactivation on card removal.
Supports asynchronous T = 0 and T =1 transmission protocols
Supports 2 –66 Mhz range for the input frequency
Supports class A, B and class AB smart cards
Timed interrupt for efficient support for synchronous protocol
Configurable depth for data path FIFO
Interrupts for all major events in hardware
Data filtering for signal integrity
C level driver for post integration SOC verification
Technology independent
Programmable timing parameters
Deliverables
Verilog RTL
Verification environment
Testcases
Synthesis environment/scripts
User manual
Verification guide
Design document
