Description
The Verification IP (VIP) for JESD403 provides an efficient and simple way to verify the JESD403 bidirectional two-wire serial interface. The VIP is fully compliant with version 1.0 specifications. JESD403 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env JESD403 VIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Features
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Compliant with JESD403 version 1.0 specification.
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Full JESD403 Host Controller and Device functionality.
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Two wire serial interfaces up to 12.5 MHz.
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Supports Dynamic Address Assignment including Static Addressing for legacy I2C Devices.
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In-Band Interrupt support.
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Support for all JESD403 Common Command Codes (CCC's).
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7-bit configurable Slave Address.
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Supports HOST DEVICE ADDRESS.
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Supports Timed reset.
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Supports Write/Read formats.
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Supports PEC enable/disable.
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Master SCL clock stalling is supported.
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Slave supports control of response fields including NACK, Data and Slave busy.
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Supports slave error types S1 and S2.
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Supports injection of various errors. • Master aborting in middle of access • Master doing ACK on last read access
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Call-backs in Master, Slave and Monitor for user processing of data
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Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
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Functional coverage of complete JESD403 specs.
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JESD403 Verification IP comes with complete testsuite to test every feature of JESD403 specification.
Deliverables
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Complete regression suite containing all the JESD403 testcases to certify JESD403 Slave/Master device
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Examples showing how to connect various components and usage of Master, Slave and Monitor.
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Detailed documentation of all class, task and functions used in verification env.
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Documentation also contains User's Guide and Release notes
