Description
A programmable on-the-fly Fractional-N PLL at 800MHz is required to lock to an incoming clock source and produce an output clock available at 110nm.
Features
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Designed to be power-efficient
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Fractional Division
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High Resolution of 800MHz
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Low Jitter
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control the phase and frequency characteristics
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Programmable Loop Filter
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Lock Detection
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Small Footprint
Deliverables
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GDSII
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LVS Spice netlist
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Verilog model
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LEF for clock generator
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PLL
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User Guidelines including:
integration guidelines
layout guidelines
testability guidelines
packaging guidelines
board-level guidelines
