Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M Analog/Codec 800MHz Frac-N PLL IP Core

800MHz Frac-N PLL IP Core

Description and Features

A programmable on-the-fly Fractional-N PLL at 800MHz is required to lock to an incoming clock source and produce an output clock available at 110nm.

 

Features
  • Designed to be power-efficient
  • Fractional Division
  • High Resolution of 800MHz
  • Low Jitter
  • control the phase and frequency characteristics
  • Programmable Loop Filter
  • Lock Detection
  • Small Footprint

    Deliverables

  • GDSII
  • LVS Spice netlist
  • Verilog model
  • LEF for clock generator
  • PLL
  • User Guidelines including:
  •   integration guidelines
  •   layout guidelines
  •   testability guidelines
  •   packaging guidelines
  •   board-level guidelines