150MHz integer-N PLL IP Core

Description

A programmable on-the-fly Fractional-N PLL at 150 MHz is required to lock to an incoming clock source and produce an output clock available at 130nm.

Features

• Integer Division
• High Stability
• Designed to be power-efficient
• Low Jitter
• Programmable Loop Filter
• Lock Detection
• Small Footprint designed to be compact        

Deliverables

• GDSII
• LVS Spice netlist
• Verilog model
• LEF for clock generator
• PLL
• User Guidelines including:

  integration guidelines

  layout guidelines

  testability guidelines

  packaging guidelines

  board-level guidelines