Description and Features

An ultra-low-power programmable fractional-N at 400MHz, phase-locked loop (PLL) for frequency synthesis available at 110nm.

Features

• Integer Division
• High Stability
• Designed to be power-efficient
• Low Jitter
• Programmable Loop Filter
• Lock Detection
• Small Footprint designed to be compact  

Deliverables

• GDSII
• LVS Spice netlist
• Verilog model
• LEF for clock generator *PLL
• User Guidelines including:

  integration guidelines

  layout guidelines

  testability guidelines

  packaging guidelines

  board-level guidelines