Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M › Verification IPs › 1G Ethernet VIP

1G Ethernet VIP

Description and Features

The Ethernet 1G Verification IP is compliant with IEEE 802.3 Specification and verifies MAC-to-PHY and PHYto- MAC layer interfaces of designs with a Ethernet 1G interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. Ethernet 1G verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product. Ethernet 1G Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env Ethernet 1G Verification IP comes with optional Smart Visual Protocol Debugger, which is GUI based debugger to speed up debugging.

1G-Ethernet-VIP-silicon-proven-ip-supplier-in-china

 

Features
  • Supports 1G • Supports GMII • Supports TBI (i.e Output of 8b/10b PCS) • Supports SGMII(10M/100M/1000M) as per specification 1.8 • Supports QSGMII as per specification 1.2 • Supports USGMII as per specification 3.0 and 3.1(5G and 10G) • Supports RGMII(10M/100M/1000M),RTBI as per specification 2.0 • Supports 1000Base-KX • Supports 1GBASE-SX and 1GBASE-LX • Supports clause 73 backplane auto-negotiation or 1000Base-KX • Supports clause 37 auto-negotiation • Supports SGMII auto-negotiation • Supports QSGMII auto-negotiation • Supports USGMII auto-negotiation and packets • Supports full duplex and half duplex of operation
  • Supports G.999.1 Interface
  • Ethernet Verification IP comes with complete UNH Test suite
  • Supports the Upper layer protocols
  • Supports IP in IP and Q in Q
  • Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
  • Full support for IEEE 1588-2002 and IEEE 1588-2008
  • PCS to Serdes interface supports all widths
  • Supports CDR for serial protocols
  • Supports MDIO slave and master model as per Clause 22 and Clause 45
  • Supports Glitch insertion and detection
  • Supports Pause frame generation and detection
  • Supports all types of TX and RX errors insertion/detection at each layer.
  • Under and oversize frame.
  • CRC errors, Framing errors
  • Pause frame errors
  • Disparity and Auto-negotiation errors
  • Invalid code group insertion
  • Invalid /K/ characters insertion
  • Lane Skew insertion
  • Invalid AN sequence error insertion
  • Missing /K/ characters for packet boundries.
  • Comes with Tx BFM, Rx BFM, and Monitor
  • Monitor supports detection of all protocol violations
  • Built in coverage analysis
  • Callbacks in master and slave for various events

Deliverables

  • User's Guide and Release notes Complete regression suite containing all the testcases.
  • Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains
Request Datasheet