Description and Features
A programmable on-the-fly Fractional-N PLL at 1.5GHz is required to lock to an incoming clock source and produce an output clock available at 22nm
Features
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Up to 1.5Ghz clock output
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Wide range of multiplicand
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Small physical area
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TEST pin integrated
Deliverables
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GDSII
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LVS Spice netlist
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Verilog model
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LEF for clock generator
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PLL
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User Guidelines including:
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ntegration guidelines
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layout guidelines
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testability guidelines
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packaging guidelines
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board-level guidelines