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    USB 3.1 Gen1 Gen2 PHY IP

    OverviewFeaturesRequest Datasheet

    The PHY IP supports both USB3.1 Gen1 & Gen2.This USB3.1 Gen2 PHY IP implements USB3.1 Gen2 transceiver and can be used as host and device. PHY IP supports USB3.1 Gen2 high speed data rate up to 10Gbps with integrated mixed signal circuit, also supports Gen1 5Gbps data rate. USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technologies TSMC 28HPC+, UMC 28HPC+, SMIC 14SF+. The USB 3.1 PHY use a single efficient GDSII design that supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes. To maximize battery life in mobile applications, the USB 3.1 PHY is designed to minimize power consumption and standby current. This USB IP is the most certified USB IP solution in the industry. The USB 3.1 PHY IP is Silicon Proven and production proven including the digital controllers and vips in different applications.

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    • Compliant with USB3.1 Gen2 base specification
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • Data and clock recovery from serial stream
    • Support 8b/10b encoder/decoder (Gen1), 128/132 encoder/ decoder (Gen2) and error indication
    • Tunable receiver detection to detect worse case cables
    • Low Frequency Periodic Signaling (LFPS) transmission and reception
    • Support SSCG function to reduce EMI effects with tunable down-spread amplitude
    • Selectable TX margining, TX de-emphasis and signal swing values
    • Built-in-self-test with internal Loopback test option
    • Programmable analog circuit parameter adjustment and internal test control
    • Silicon Proven in TSMC 28nm, UMC 28nm, SMIC 14nm
    Deliverables
    • GDSII & layer map
    • Place-Route views (.LEF)
    • Liberty library (.lib)
    • Verilog behavior model
    • Netlist & SDF timing
    • Layout guidelines, application notes
    • LVS/DRC verification reports
    • Test patterns and Test Documentation
    Benefits
    • IP Module Area: 0.285mm^2
    • Supports SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps, and HighSpeed USB 2.0
    • Optimized Host, Device, and DualRole Device controller IP designed to achieve lowest power and area for portable electronics
    • Supports PIPE and UTMI+ PHY interfaces
    • Architectural features reduce power consumption
    Applications
    • Smartphones, tablets
    • Notebooks
    • USB to video display or video display adaptors
    • Docking stations
    • Storage
    • Set-top boxes
    • Smart TVs
    • Cloud computing/enterprise and server SoCs

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