SDR Gen3 RF IP (100MHz~2.6GHz) for 4G / IoT
This is the 3rd Generation Software Defined Radio (SDR) RF Transceiver IP that supports 1x1 and a frequency ranging from 100MHz to 2.6 GHz, which is currently in TSMC 40nm. The Software Defined Radio (SDR) Gen.3 supports the ADC/DAC with 80Msps sampling speed. The SDR RF IP also supports TDD/HD-FDD and is optimized for IoT applications
This Software Defined Radio (SDR) RF Transceiver IP family are ultra-low-power radio solutions optimized from IoT and M2M to 5G applications. They integrate all the necessary RF/analog/mixed-signal functions to support radio functions for most standards operating in this frequency range at low-cost and ultra-low-power.
The receive path (RX) has very high dynamic range and is implemented with direct-conversion architecture without external SAW filter. A direct conversion TX generates low EVM signals to drive the external power amplifier. An integrated Frac-N frequency synthesizers and LO-chains generate the required low phase-noise LO signals for TX and RX mixers. Optional fully integrated power management can be integrated to minimize the module eBOM cost.
This unique Software Defined Radio (SDR) RF Transceiver IP family support many wireless market standards, including: 5G, Wi-Fi, LTE, NB-IoT, 802.15.4g, 802.11ah, Bluetooth, LORA, GNSS/GPS among others. This ultra-low-power transceiver IP enables Internet-of-Things (IoT) and Machine-to-Machine (M2M) applications.
The other generation of the Software Defined Radio (SDR) RF Transceiver IP are as follows:
● SDR1: TSMC65, 1x2 300MHz – 2.8GHz, up to 40MHz bandwidth, up to 160/640MSPS ADC/DAC
● SDR2: TSMC65, 2x2, 100MHz-3.8GHz, up to 120MHz bandwidth, 160/640 MSPS ADC/DAC, FD-FDD
● SDR4: TSMC22, 200MHz ̴7.3GHz, (2022 sampling), TDD/FD-FDD
- Frequency Range: 100MHz - 2.6GHz
- Bandwidth Range: 180KHz ~ 20MHz
- Supports HD-FDD/TDD modes.
- Low phase-noise Frac-N synthesizer
- Fast PLL for frequency hopping
- Modulation Support: OFDM, QPSK, QAM, OQPSK
- Transmit power: +23 dBm
- Integrated DPD to improve Tx power efficiency and linearity.
- ADC/DAC: 10/12bit SAR 80/160 Msps
- Integrated LDOs and DC-DC
- Low Rx. Power: ~ 10mW (w/o LDO mode)
- Silicon : TSMC 40ULP
- Power Supply Voltage: VDDH=3.3V
- VDDL=0.95V (1.2V if internal LDOs are used.)