H.264, also known as MPEG-4 Part 10, is a widely used industry standard for video compression, succeeding earlier standards like MPEG-2 and MPEG-4. It offers highdefinition video compression, delivering MPEG-4 quality at significantly larger frame sizes and MPEG-2 quality at reduced data rates, making it ideal for various resolutions from 320x240 to 4K. The standard supports encoding settings for 30FPS and 60FPS, with maximum resolution capabilities of 5440x4080. H.264 compression can be implemented on various FPGA platforms from vendors like Xilinx, Altera, Lattice, and Microchip, requiring FPGAs with sufficient LUTs and dual-port memory. Deliverables for implementing H.264 compression include a netlist, a user manual, sample VHDL code, and synthesis scripts. Test cases demonstrate the efficiency of H.264 compression, achieving high compression ratios, such as 97.1% for 4K resolution, with a compression time of approximately 247 seconds using a 100 MHz clock.
Clock
1 Clock at 100 MHz and 1 Clock at 50 MHz
Encoding Settings
Support 30FPS and 60 FPS. Different Video Size:
Max Resolution (5440X4080) Standard 4K Definition (3840X2160) Full High Definition (1920 x 1080)
Commonly Used High Definition (1280 x 720) Standard Definition (640 x 480)
Internet-size Content (320 x 240) The resolution can be customize
Supported FPGAs
Any FPGA with sufficient number of LUTs and Dual-Port memory
FPGA families from the following vendors: Xilinx (AMD), Altera (Intel), Lattice, Microchip
Some examples Test 1: H264 YUV 4:2:2 compression:
Input video:
resolution: 352x288
Video format: YCbCr 4:2:2, 16 bits
Frame number = 90
Size = 18 247 680 bytes (352*288*16bits*90frames)
Output video:
resolution: 352x288
Size = 1 786 013 bytes
Compression ratio = 90,2%
Full compression time = approximatively 310 ms
Test 2 :H264 YUV 4:2:2 4K compression:
Input video:
resolution: 4K (3840x2160)
Video format: YCbCr 4:2:2, 16 bits
Frame number = 900
Size = 14 929 920 000 bytes (3840*2160*16bits*900frames)
Output video:
resolution: 4K (3840x2160)
Size = 427 798 526 bytes
Full compression time = approximatively 247s with 100 Mhz clock
Compression ratio = 97,1%
Deliverables
Netlist for FPGA family and memory
User’s manual
Sample VHDL code that incorporates the core
Synthesis script for sample code