The H265 HEVC video encoder IP core is a single-chip solution designed to support H.265 video encoding across various resolutions, including QVGA, SD, HD up to 1080p@120, and 4K@60, with future support planned for 8K@60. Currently, it supports up to 1080p@60 and 4K@60, and is compatible with FPGAs from both Xilinx and Intel, including the Xilinx Zynq-7000 and Intel Arria-10 series. The encoder supports Main 4:2:2 at 10 bits, with options for encoding 4:2:0 or 4:2:2 streams, and is available in 8-bit and 10- bit profiles, catering to both consumer products and high-end applications like broadcast and medical devices. It comes with a user API for controlling encoder operations, and is offered in various versions: Standard, I-Frame, Slim, and other specialized versions for multi-channel and 3D HD TV applications.
Video: H.265/HEVC (ISO/IEC 23008-2:2015)
Audio: HE-AAC (ISO/IEC 14496-3)
Main 4:2:2 10
Chroma format : 4:2:0 4:2:2
Precision : 8 bits 10 bits
Frame Rate : 10fps ,24fps,25fps ,29.97fps,30fps 30fps,50fps,59.95fps,60fps,120fps
Inter frames: I frame I&P frame
Audio Sample rate : 32kHz,44.1kHz and 48 kHz
Audion Bit Rate : 16-18 kbps(32kHz), 16-36 kbps (44.1kHz and 48 kHz
Output Stream Format: Constant Bit Rate (CBR) – User controllable through API Variable Bit Rate (VBR) – User controllable through API.
Logic Resource Consumption (Xilinx FPGAs): Standard Version: 200k LUTs, 10Mb of Block RAM, 630 DSPs I-Frame Version: 140k LUTs, 3Mb Block RAM, 630 DSPs
Logic Resource Consumption (Intel FPGAs): Standard Version: 150kALMs, 10Mb of Block RAM, 630 DSPs I-Frame Version: 110kALMs, 3Mb Block RAM, 630 DSPs
Deliverables
Netlist for FPGA family and memory
User's manual
Sample VHDL code that incorporates the core
Synthesis script for sample code
Simulation and verification testbench
