Description
The GPIO Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The GPIO Controller IP can be implemented in any technology. The GPIO Controller IP core supports the standard protocol of GPIO specifications. GPIO Controller IP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, AXI, Wishbone, VCI, Avalon, PLB, Wishbone or custom buses.
Features
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Compliant with standard protocol of GPIO specification
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Supports configurable for GPIO pins from 1 to 32 bits
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Supports dynamic programming of each GPIO bit as input or output
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Supports optional interrupt generation with configurable edge detection of the inputs (Either Rising/Falling edge)
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Fully synthesizable.
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Static synchronous design.
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Positive edge clocking and no internal tri-states.
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Scan test ready.
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Simple interface allows easy connection to Microprocessor/Microcontroller devices
Deliverables
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RTL design in Verilog
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Lint, CDC, Synthesis Scripts with waiver files
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Lint, CDC, Synthesis Reports
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Technical documentation in greater detail
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Easy to use Verilog Test Environment with Verilog Testcases
