The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet application with low power consumption. It supports 10BASE-T, 100BASE-TX, 1000BASE-T operation. This GPHY connects the Media Access Control Layer (MAC) by GMII (Giga Media Independent Interface). This GPHY connects the Media Access Control Layer (MAC) by GMII (Giga Media Independent Interface) or RGMII. it could support Un-shielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet and 1000BASE-T Giga Ethernet, or UTP5/UTP3 cable for 10BASE-Te Ethernet. It contains the entire physical layer function of 100BASE-TX defined by IEEE802.3u and 1000BASET defined by IEEE 802.3ab, including the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), Twisted Pair Physical Medium Dependent Sub-layer (TP-PMD, 100BASE-TX only).
IEEE 802.3-2008, IEEE 802.3az fully standards compliant
IEEE 1588-2008 support
BroadR-Reach™ support
Dual port MAC interface:
GMII (10/100/1000BASE-T)
MII (10/100BASE-T)
Auto-negotiation support
Automatic detection and correction of pair swaps (Auto-MDIX), pair skew and pair polarity
6 different operating modes:
1000BASE-T Full Duplex and Half Duplex
100BASE-TX Full Duplex and Half Duplex
10BASE-T Full Duplex and Half Duplex
Management interface
Baseline wander compensation
On-chip transmit wave-shaping
On-chip hybrid circuit
10KB jumbo frames
Internal, external and remote loop back
Hardware configuration for default operation
Power down mode, interrupt support
IEEE 1500 support for SoC testing integration
LED indication: link mode, status, speed, activity and collision
Silicon Proven in ST 28nm FDSOI
Deliverables
Detailed Datasheet
Verilog behaviour model (A) for simulation
Liberty (db./.lib) for synthesis, STA, and equivalence checking
CTL / CTLDB for DFT
SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
LEF for APR
CDL for LVS connection
