Your Complex IP Core Partner

    GbE (10/100 Base-Tx) PHY IP

    OverviewFeaturesRequest Datasheet

    Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver for 10BASE-Te, 100BASE-TX, operation. Through the Giga Media Independent Interface (GMII), the EPHY connects to the Media Access Control Layer (MAC), and on the media side, it provides a direct interface either to Un-shielded Twisted Pair Category 5 Cable(UTP5) for 100BASE-TX Fast Ethernet or UTP5/UTP3 cable for 10BASE-Te Ethernet. The Ethernet PHY employ a low power and high performance CMOS process. It contains the entire physical layer function of 100BASE-TX defined by IEEE802.3u, including the Physical Coding Sub-layer(PCS), Physical Medium Attachment Layer(PMA), Twisted Pair Physical medium Dependent Sub-layer (TP-PMD, 100BASE-TX only). The EPHY also provide a robust auto-negotiation function, utilizing automatic media speed/duplex and protocol selection match. EPHY also support Auto MDI/MDIX function to simplify the network installation.

    t2m-design-reuse t2m-chipestimate t2m-anysilicon
    • Fully compliant with the IEEE 802.3 / 802.3u
    • 10BASE-Te, 100BASE-TX
    • Interface available to Compliant with TP-PMD standard: ANSI X3.263-1995
    • Compliant with FDDI-PMD standard: ISO/IEC 9314-3: 1990 and ANSI X3.166-1990
    • Support GMII interface to the MAC controller.
    • Serial management interface compliant with IEEE 802.3u (MDIO)
    • Support Full-Duplex or Half-Duplex Operation
    • Support Auto-Negotiation Next Page /Parallel Detection function
    • Compliant with IEEE 802.3u, and Manual configuration is also supported.
    • Automatic Polarity Correction
    • Support auto MDI/MDIX crossover function for 10BASE-Te / 100BASE-TX
    • High performance baseline wander correction (BLW) Circuit
    • High Performance Digital Clock recovery algorithm
    • High performance Digital Equalizer for ISI mitigation
    • LED Driver for Link, Activity, Duplex, Collision, and Speed Status
    • Low Power design, with support 803.2az standard-2010 (EEE)
    • Support MAX 300ppm sampling offset
    • Silicon Proven in UMC 28HPC, UMC 40LP
    • Detailed Datasheet
    • Verilog behavior model (A) for simulation
    • Liberty (db / .lib) for synthesis, STA, and equivalence checking
    • CTL / CTLDB for DFT
    • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
    • LEF for APR
    • CDL for LVS connection
    • Network Interface Adapter
    • Embedded system with an Ethernet MAC that needs a UTP physical connection
    • Such as, STB, IP STB, Fiber IP STB, etc.,
    • Ethernet Hub
    • LANs (Local Area Networks).
    • Sensor and monitoring interfaces.
    • Security and surveillance.
    • Building automation.
    • Transportation systems.

      Fill the form below, to receive the product datasheet in your inbox