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    eDP Receiver Controller IP

    OverviewFeaturesRequest Datasheet
    The eDP Receiver IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eDP Receiver IP can be implemented in any technology. The eDP Receiver IP core supports the eDP 1.4b specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The eDP Receiver II is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eDP Receiver IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.     eDP-receiver-controller-silicon-proven-ip-provider-in-china     Related Links: Design & Reuse | ChipEstimate | Anysilicon

    Features

    • Supports eDP 1.4b specification
    • Supports full eDP Receiver functionality
    • Supports multi lanes upto 4 lanes.
    •  Supports main link, Aux link and Hot plug functionality.
    •  Supports packing of all the video formats supported by the display port
    •  Supports HPD based link training
    •  Supports deskew in sink device mode
    •  Supports scrambler as in Display port specification
    • Supports scrambler reset after every 512th symbols.
    • Supports RGB, YCBCR444, YCBCR422, YCBCR420, Y-Only and RAW color format.
    • Supports PSR (Panel Self Refresh) entry and exit.
    • Supports frame number identification in PSR.
    •  Supports Selective update (partial frame update) during Panel Self Refresh (PSR)
    • Supports PSR2(Panel Self Refresh) as per spec eDPv1.4b
    • Supports Multi SST operation(MSO) Two SST Links with one Lane each (two Lanes total), 2x1 Two SST Links with two Lanes each (four Lanes total), 2x2 • Four SST Links with one Lane each (four Lanes total), 4x1
    • Supports Advanced Link Power Management to reduce wake latency
    •  Supports GTC-based video timing synchronization
    •  Supports Display stream compression as per spec eDPv1.4b
    • Supports PSR Secondary Data Packet.
    •  Supports Display Backlight Control Using DPCD Registers.
    • Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
    • Supports high-bandwidth Digital Content Protection System version1.3 (HDCP v1.3)
    • Supports high-bandwidth Digital Content Protection System version2.2 (HDCPv2.2) • Supports for HDCP2.2 with full authentication Supports for HDCP2.2 with bypass the authentication
    • Supports high-bandwidth Digital Content Protection System version2.3 (HDCPv2.3)
    • Fully synthesizable
    • Simple interface allows easy connection to microprocessor/microcontroller devices

    Deliverables

    • RTL design in Verilog.
    • Lint, CDC synthesis script with waiver files.
    •  Lint, CDC synthesis reports.
    •  IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Technical documentation in greater detail.
    • Easy to use Verilog test environment with Verilog test cases.

    Benefits 

    • Fully compliant, silicon-proven core
    •  Comes with Verilog testbench and option to buy full advanced System Verilog Testbench
    • Support directly from engineer who designed the code
    •  Based on RMM (Re Use Methodology Manual guidelines)
    • Supports all the Synthesis tools

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