Select Language

Your Complex IP Core Partner

    PCIe 2.0 SerDes PHY IP

    OverviewFeaturesRequest Datasheet

    The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base specifications, the PHY IP integrates mixed-signal circuits to support both 2.5GT/s and 5.0GT/s data transmission rates. The PCIe2.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.

    The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area (sub-0.30mm2), without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.

      pcie-2-phy-serdes-ip-silicon-proven-ip-core-provider-in-Japan  
    t2m-design-reuse t2m-chipestimate t2m-anysilicon

    • Compliant with PCIe2.0 specification
    • Standard PHY interface (PIPE) enables multiple IP sources for PCIe2.0 MAC layer
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • 8b/10b encoder/decoder and error indication
    • Tunable Receiver detection to detect worse case cables
    • Beacon signal transmission and reception in PCIe mode
    • Supports SSC to reduce EMI effects with tunable down-spread amplitude
    • Selectable TX margining, Tx de-emphasis and signal swing values
    • Internal Loopback Test Capable
    • Allowable analog circuit parameter adjustment and internal test control
    • Built-in Self Test with embedded Jitter Injection
    • Output Jitter reduction with constant power technique
    • Automatic De-skew adjustment
    • Support Silicon Proven in TSMC 28HPC
    • Support Silicon Proven in TSMC 22ULP/ULL
    • Support Silicon Proven in TSMC 55ULP / 65ULP
    • Support Silicon Proven in SMIC 40LL
    • Suppport Silicon Proven in SMIC 55LL/ SP/ EF
    • Support Silicon Proven in UMC 28HPC
    • Support Silicon Proven in UMC 40LP
    • Equipped with Pulse Current Injection Pre-Charge for TX Eye
    Benefits
    • Build in Self test with embedded jitter injection
    • Jitter reduction with constant power technique
    • Automatic Deskew adjustment
    • Output Jitter reduction with constant power technique
    • Internal Loopback Test Capable
    Applications
    • PC
    • Television
    • Data storage
    • Multimedia Devices
    • Recorders
    • Mobile devices
    Deliverables
    • GDSII & layer map
    • Place-Route views (.LEF)
    • Liberty library (.lib)
    • Verilog behavior model
    • Netlist & SDF timing
    • Layout guidelines, application notes
    • LVS/DRC verification reports

      Fill the form below, to receive the product datasheet in your inbox