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    USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP

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    The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

    t2m-design-reuse t2m-chipestimate t2m-anysilicon
    • Compatible with PCIE/USB3/SATA base Specification
    • Fully compatible with PIPE3.1 interface specification
    • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
    • Support 20-bit parallel interface when encode/decode bypassed
    • Support flexible reference clock frequency
    • Support 100MHz differential reference clock input or output (optional with SSC) in PCIE Mode
    • Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm
    • Support programmable transmit amplitude and De-emphasis
    • Support TX detect RX function in PCIE and USB3.0 Mode
    • Support Beacon signal generation and detection in PCIE Mode
    • Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
    • Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode
    • Support L1 sub-state power management
    • Support RX low latency mode in SATA operation mode
    • Support Loopback BERT and Multiple Pattern BIST Mode
    • Process: TSMC28nm Logic HPC Plus 0.9V/1.8V 1P8M
    • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
    • Application Note / User Manual
    • Behavior model, and protected RTL codes
    • Protected Post layout netlist and Standard
    • Delay Format (SDF)
    • Synopsys library (LIB)
    • Frame view (LEF)
    • Metal GDS (GDSII)
    • Test patterns and Test Documentation
    • IP Area: 0.244mm^2
    • USB 3.0 SuperSpeed
    • SATA gen1/2/3 Transmission schemes encoding octets a 10-bit code groups to form a DC-balanced stream
    • High-performance backplane interconnect
    • Supports PCIe base specifications
    • Supports USB base specifications
    • Supports SATA base specifications
    • PC
    • Television
    • Data storage
    • Multimedia Devices
    • Recorders
    • Mobile devices

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