Description
The Network Interconnect (NIC) IP is a silicon proven, scalable on-chip interconnect solution designed to connect CPUs, GPUs, accelerators, and peripherals in complex SoCs. Built on distributed Network-on-Chip (NoC) technology, it acts as a a hardware/software set of services. It supports AXI3, AXI4, and ACE-L protocols with high interoperability, delivering performance, power efficiency, and flexible scalability for medium to high-complexity SoCs.
NIC Technology can be used in both high and medium complexity SoC interconnect, thanks to its capability to scale the implementation cost depending on the target functionalities and performances.
Features
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AXI4 IP (32,64,128 bits) protocol support and interoperability with AXI3.
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ACE-L IP protocol support and interoperability.
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Integrated Trace & Debug (TnD) with WatchPoint for pattern detection.
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On-chip interconnect debug technology (SBAG) replacement.
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Built-in safety and fault-tolerant mechanisms for interconnect configuration.
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Can be mixed with other interconnect technologies like STBus, ARM NiC400/CCI-400.
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Read Data Interleaving support to have 100% compliance with ARM CCI400.
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Can be deployed in both the main backbone interconnect and the local subsystem interconnects.
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Supports NoC Control Unit to simplify the NoC configuration and SW view.
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Outperforms traditional crossbar-based matrices in complex SoCs.
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Implements medium complexity interconnect with comparable performance/area efficiency of AMBA matrices.
Deliverables
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Extensive Product Documentation
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Verilog Model (A) for Simulation Purposes
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Liberty Database (.db/.lib) for Synthesis, Timing Analysis, and Equivalence Verification
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Design Verification with CTL/CTLDB Techniques
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ATPG Utilizing SPF (STIL Procedure File)
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Layout Exchange Format (LEF) for Automated Place and Route (APR)
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Circuit Description Language (CDL) for Layout Versus Schematic (LVS) Alignment
