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Ethernet 10G KR PCS IP

Description and Features

The Ethernet 10G KR PCS IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 10G KR PCS IP can be implemented in any technology. The Ethernet 10G KR PCS IP core supports Ethernet protocol standard of IEEE 802.3.201 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses . The Ethernet 10G KR PCS IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 10G KR PCS IP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

 

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Features
  • IEEE Standard 802.3.2018 Clause 49 for Base R PCS
  • Supports 64b/66b encoding and decoding for transmit and receive path
  • Supports data scrambling on the transmit path and descrambling on the receive path
  • Supports gearbox for various XSBI data width
  • Supports Block synchronization
  • Supports Bit Error Rate monitoring
  • Supports receiver Link fault status detection
  • Supports Loopback functionality
  • Supports for IEEE 802.3az Energy Efficient Ethernet.
  • Supports Configurable Management Interface (MDIO - Clause 45 / SOC Bus)
  • Supports XSBI Interface for the following data widths,• 16 Bits• 20 Bits• 32 Bits• 40 Bits• 64 Bits
  • Optional support for Forward error correction as per clause 74 of IEEE Standard 802.3.2018
  • Optional support for Test pattern generation and error checkers
  • Optionally supports auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
  • Optionally supports link training as per clause 72 of IEEE Standard 802.3.2018
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Deliverables

  • RTL design in Verilog
  • Lint, CDC, Synthesis Scripts with waiver files
  • Lint, CDC, Synthesis Reports
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Technical documentation in greater detail
  • Easy to use Verilog Test Environment with Verilog Testcases
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