Ethernet 50G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 50G PCS IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
Supports IEEE Standard 802.3.2018
Supports 50G BASE-R
Supports 50G BASE KR2/CR2
Supports 64b/66b encoding and decoding for transmit and receive path
Supports data scrambling on the transmit path and descrambling on the receive path
Supports Lane Distribution across 4/2 Lanes for 50Gpbs
Supports Block synchronization
Supports gearbox for various data width
Supports Alignment Marker insertion and removal
Support PCS Lane Deskew
Supports BIP-8 insertion on transmit path and checking on receive path per lane
Supports Bit Error Rate monitoring
Supports receiver Link fault status detection
Supports Loopback functionality
Supports for IEEE 802.3az Energy Efficient Ethernet.