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GDDR4 Controller IP

Description and Features

GDDR4 interface provides full support for the GDDR4 interface, compatible with GDDR4Spec_rev_04 specification and DFI-version 4.0 or 5.0 Specification Compliant. Through its GDDR4 compatibility, it provides a simple interface to a wide range of lowcost devices. GDDR4 IP is proven in FPGA environment. The host interface of the GDDR4 can be simple interface or can be AMBA AHB, AMBA AHBLite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

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Features
  • GDDR4 protocol standard GDDR4Spec_rev_04.
  • Compliant with DFI-version 4.0 or 5.0 Specification.
  • Supports all the GDDR4 commands as per the specs.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels
  • Supports in port arbitration and multi-port arbitration.
  • Supports user programmable page policy. • Closed page policy • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports for programmable clock frequency of operation.
  • Supports for all types of timing and protocol violation detection.
  • Supports for All Mode registers programming.
  • Supports for Double data rate architecture.
  • Supports for Single ended READ strobe (RDQS) per byte.
  • Supports for Single ended WRITE strobe (WDQS) per byte.
  • Supports for Quad or eight internal banks for concurrent operation.
  • Supports for Bidirectional differential data strobe.
  • Supports for Programmable Burst Length: 8 only.
  • Supports for Data mask (DM) for masking WRITE data.
  • Supports for Multiplexed addressing.
  • Supports for Auto Precharge option for each burst access.
  • Supports for Auto Refresh and Self Refresh Modes.
  • Supports for On-die termination (ODT).
  • Supports for Programmable offset for both driver and termination.
  • Supports for Parity and Boundary Scan (both optional).
  • Supports for input clock stop and frequency change.
  • Positive edge clocking and no internal tri-states.

Deliverables

  • The GDDR4 interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.
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