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MIPI ASPMI Slave Controller IP

Description and Features

MIPI ASPMI Slave interface provides full support for the two-wire MIPI ASPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI ASPMI Slave IP is proven in FPGA environment. The host interface of the MIPI ASPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXl-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol. MIPI ASPMI Slave IP is supported natively in Verilog and VHDL

 

Features
  • Compliant with 5 ASPMI Slave Specification
  • Full MIPI SPMI Slave functionality
  • Supports following frames • Command Frame • Data/Address Frame • No Response Frame
  • Supports ACK/NACK as per 0 specs
  • Support for slave requests through Alert(A) / Slave Request (SR) bit
  • Support for Slave Request
  • Glitch suppression (optional).
  • Supports extended register read/writes
  • Supports wakeup command
  • Supports Authentication Command Sequence
  • Supports Device Descriptor Block Command Sequences
  • Supports following Device Interrupts • Edge sensitive interrupts • Level sensitive interrupts a Group interrupts • SPS (System Power State) interrupts • DVC Group interrupts • LDO and DVC interrupts • Interrupt priority queuing • IRQH Enable register (Disabling of IRQ generation functionality based on NACK Retry limit) • Generation of Group event on any internal SPMI error logged in an ERROR CTRL register
  • Supports virtual wires on SPMI (Supports both scheme 1 and scheme 2)
  • Supports Short Addressing Modes
  • Supports Control on Register0 write and power mode command (Sleep/Wakeup/Shutdown/Reset) reception
  • Supports Slave To Slave (STS) Transmit and Receive Command filtering
  • Ability to generate an empty arbitration request
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices

Deliverables

  • The MIPI ASPMI Slave interface is available in Source and netlist
  • The Source product is delivered in plain text If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release
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