This RF transceiver IP is the design data base of a WiFi Dual Band RF Transceiver extracted from a 55nm production chip shipped in Tier 1 handsets. The RF Architecture gives highest level of integration and optimized for low power consumption. A single RF LC oscillator PLL provides the quadrature LO signals to the low and high band up and down converters.
The low and high band signals are demodulated by separate RF front ends. The radio signal from the balanced 2.4 GHz or 5 GHz RF input is amplified by the low band or high band LNA. The digital modem implements the OFDM and DSSS/CCK modulation for all frame-formats specified for a single layer/transmitter. The OFDM and DSSS/CCK modulated I/Q signals use a common circuit for digital up-sampling, filtering, quadrature imbalance compensation, LO leakage correction, and digital power scaling.
The RF design incorporates best in class cellular blocker tolerance & transmit emissions in cellular bands. PTA/ e-PTA with BT.
High Volume Silicon Proven in 55nm
Extracted from Design Data Base of production chip
Dual Band 2.4/5 Ghz20MHz RF transceiver with integrated PA & Balun
Digital interface through integrated AFE (ADC/DAC)
Best-in-class IOT with comprehensive coverage
Ultra-low power consumption with innovative host offloading features
RF design includes best in class cellular blocker and innovative LTE & BT Co-Existence
Certified in Tier 1 handset shipped in high volume
Tx Power: +19.5dBm at Antenna (2.4GHz)
Rx Sensitivity: -97dBm
Source Code of Design Data Base with rights to modify