MIPI I3C IP
I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products. Our I3C supports several communication formats all sharing a two wire interface – SDA and SCL. SDA is a bidirectional data pin while SCL can be either a clock pin or a data pin while in HDR mode. The type of communication supported by I3C
I2C-like communication with SCL clock speed up to 12.5 MHz , MIPI-defined transmissions that allow the master to communicate to one or all slaves on the bus. HDR mode using ternary number symbols to achieve two data transmissions per equivalent clock cycle. A subset of I2C communication to legacy I2C slaves, if present on the bus. Slave initiated request to master, e.g. In-band interrupt, address request.
- Compliant with the MIPI Alliance
- Draft Specification for I3C Version 0.5 Revision 1
- I3C Master Features
- Supports all modes of Master – SDR, HDR and HDR-DDR,I2C Modes
- Can be configured to work as secondary master also.
- Dynamic addressing assignment capability
- Support for slave generated in band interrupts.
- Memory for retaining bus device addresses.
- I3C Slave Features
- Supports I3C slave configuration – HDR-DDR Slave, SDR Only Slave.
- Common Slave IP can be instantiated many times to have multiple slaves on the I3C bus.
- Dynamic address complaint.
- Supports/Tolerate I3C global command codes.
- Master Interface for system access : APB. Optionally AXI.
- Slave Interface for Register access : APB
- Configurable FIFOs
- I3C Master Can be configured to work as secondary master.
- I3C Slave configuration – HDRDDR Slave, SDR only Slave.
- System Access: APB or AXI
- Configurable FIFO’s
- Highly modular and configurable design
- Supports both sync and async reset
- Software control for key features
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Design Guide
- Verification Guide
- Synthesis Guide